Topic on Glossary talk:Overclocking
This page shows the changes between two versions of a post by Mirh in the topic "Wisdom infodump" on Glossary talk:Overclocking.
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* [https://www.notebookcheck.net/Intel-Extreme-Tuning-Utility-XTU-Undervolting-Guide.272120.0.html XTU] and [https://www.ultrabookreview.com/31385-the-throttlestop-guide/ ThrottleStop], end. | * [https://www.notebookcheck.net/Intel-Extreme-Tuning-Utility-XTU-Undervolting-Guide.272120.0.html XTU] and [https://www.ultrabookreview.com/31385-the-throttlestop-guide/ ThrottleStop], end. | ||
* Well, not so fast. The Plundervolt attack made Intel recommend vendors to enable the "Overclocking Lock" flag in the bios (which, despite the name, at least on normal locked cpus just allowed for voltage control). It [https://old.reddit.com/r/XMG_gg/comments/h0wuoh/cpu_undervolting_in_bios_setup_for_xmg_and/ wasn't] a ''hard'' requirement.. but this was just the path of least resistance for most. It's not really difficult to unlock with the usual [[Glossary talk:BIOS|bios tools]], but still. | * Well, not so fast. The Plundervolt attack made Intel recommend vendors to enable the "Overclocking Lock" flag in the bios (which, despite the name, at least on normal locked cpus just allowed for voltage control). It [https://old.reddit.com/r/XMG_gg/comments/h0wuoh/cpu_undervolting_in_bios_setup_for_xmg_and/ wasn't] a ''hard'' requirement.. but this was just the path of least resistance for most. It's not really difficult to unlock with the usual [[Glossary talk:BIOS|bios tools]], but still. | ||
− | * [https://old.reddit.com/r/overclocking/comments/ls3yqo/help_with_understanding_bd_prochot/ BD PROCHOT] misbehaving can explain "cold temperature" throttling | + | * [https://old.reddit.com/r/overclocking/comments/ls3yqo/help_with_understanding_bd_prochot/ BD PROCHOT] misbehaving or [https://superuser.com/questions/1465350/how-to-determine-processor-frequency-scale-down-to-200-mhz-due-to-thermstatus/#1669682 errata] can explain "cold temperature" throttling |
+ | * For Turbo Boost to consider a core inactive this has to be [https://web.archive.org/web/20120131091738fw_/https://download.intel.com/design/processor/applnots/320354.pdf at least] in C3 sleep, so (at least on non-K cpus [https://gearspace.com/board/music-computers/465221-c1e-c3-c6-eist-speedstep-turbo-boost-core-parking-3.html#post6298060 normally]?) in order to retain maximum few-threaded performance with minimum latency you'd need core pinning and manual fine-tuning of individual per-CPU-registers. | ||
'''General''' | '''General''' |